Prof. Yasuo Arai: Development of Silicon-on-Insulator pixel detector, ELI-NP, Friday, 7 July 2017, 10:00 - 10:45 am

General Seminar

Friday, 7 July 2017, 10:00 - 10:45 am

Big Meeting Room, ground floor, ELI-NP Building

Title: "Development of Silicon-on-Insulator pixel detector"

Lecturer: Prof. Yasuo Arai

Advanced monolithic pixel process and detectors were developed by using a Silicon-On-Insulator (SOI) technology.
The SOI technology uses bonded wafer of two silicon substrate sandwiching a thin oxide layer. Bottom silicon of the wafer works as thick fully-depleted sensors and top thin Si-layer contains CMOS readout circuits.
Although there were several difficult issues to realize the SOI detector, we have solved such issues by developing new technologies such as buried well and double SOI wafer/process.
Recently we could achieve 0.7 um position resolution for high-energy charged particle tracking for the first time in the world. As for X-ray spectroscopy, 10 electron noise level is achieved for 6keV X-ray. The process technologies and several examples of SOI detectors are presented.